This research is my senior design project.
Research resistive RAM (ReRAM) memory cell arrays, focusing on unexpected behavior induced between neighboring cells in a crossbar architecture. Start by using previously designed infrastructure to heat a cell, while measuring the electrical characteristics of its neighboring cells. Then, analyze the results, investigating the cell array limitations. Finally, refine the measuring infrastructure, research goals, and analysis method. The resulting cell limitation analysis will provide a broader ReRAM understanding to progress the memory chip industry.
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